.. DO NOT EDIT. .. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY. .. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE: .. "examples/folding_example_with_architecture.py" .. LINE NUMBERS ARE GIVEN BELOW. .. only:: html .. note:: :class: sphx-glr-download-link-note :ref:`Go to the end ` to download the full example code. .. rst-class:: sphx-glr-example-title .. _sphx_glr_examples_folding_example_with_architecture.py: ======================= Comparison with folding ======================= This is a common example when illustrating folding. In general, the main problem with folding is to determine a suitable folding order. This corresponds to scheduling the operations. Here, the folding order is the same for the adders as in the standard solution to this problem, but the order of the multipliers is different to keep each memory variable shorter than the scheduling period. .. GENERATED FROM PYTHON SOURCE LINES 16-39 .. code-block:: Python from b_asic.architecture import Architecture, Memory, ProcessingElement from b_asic.core_operations import Addition, ConstantMultiplication from b_asic.schedule import Schedule from b_asic.scheduler import ASAPScheduler from b_asic.sfg import SFG from b_asic.special_operations import Delay, Input, Output in1 = Input("IN") T1 = Delay() T2 = Delay(T1) a = ConstantMultiplication(0.2, T1, "a") b = ConstantMultiplication(0.3, T1, "b") c = ConstantMultiplication(0.4, T2, "c") d = ConstantMultiplication(0.6, T2, "d") add2 = a + c add1 = in1 + add2 add3 = b + d T1 <<= add1 out1 = Output(add1 + add3, "OUT") sfg = SFG(inputs=[in1], outputs=[out1], name="Bi-quad folding example") .. GENERATED FROM PYTHON SOURCE LINES 40-41 The SFG looks like: .. GENERATED FROM PYTHON SOURCE LINES 41-43 .. code-block:: Python sfg .. raw:: html
%3 in0 IN (in0) add0 add0 in0->add0 0 add0.0 add0->add0.0 out0 OUT (out0) add2 add2 add2->out0 add1 add1 add1->add0 1 add0.0->add2 0 t0 t0 add0.0->t0 t0.0 t0->t0.0 add3 add3 add3->add2 1 cmul0 b (cmul0) cmul0->add3 0 cmul1 d (cmul1) cmul1->add3 1 t1.0 t1.0->cmul1 cmul2 c (cmul2) t1.0->cmul2 t1 t1 t1->t1.0 t0.0->cmul0 t0.0->t1 cmul3 a (cmul3) t0.0->cmul3 cmul2->add1 1 cmul3->add1 0


.. GENERATED FROM PYTHON SOURCE LINES 44-45 Set latencies and execution times .. GENERATED FROM PYTHON SOURCE LINES 45-50 .. code-block:: Python sfg.set_latency_of_type(ConstantMultiplication, 2) sfg.set_latency_of_type(Addition, 1) sfg.set_execution_time_of_type(ConstantMultiplication, 1) sfg.set_execution_time_of_type(Addition, 1) .. GENERATED FROM PYTHON SOURCE LINES 51-52 Create schedule .. GENERATED FROM PYTHON SOURCE LINES 52-55 .. code-block:: Python schedule = Schedule(sfg, scheduler=ASAPScheduler(), cyclic=True) schedule.show(title='Original schedule') .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_001.png :alt: Original schedule :srcset: /examples/images/sphx_glr_folding_example_with_architecture_001.png :class: sphx-glr-single-img .. GENERATED FROM PYTHON SOURCE LINES 56-57 Reschedule to only require one adder and one multiplier .. GENERATED FROM PYTHON SOURCE LINES 57-70 .. code-block:: Python schedule.move_operation('out0', 2) schedule.move_operation('add2', 2) schedule.move_operation('cmul2', -3) schedule.move_operation('add3', 3) schedule.move_operation('cmul1', -3) schedule.set_schedule_time(4) schedule.move_operation('cmul1', 1) schedule.move_operation('cmul0', 1) schedule.move_operation('in0', 3) schedule.move_operation('cmul2', -1) schedule.move_operation('cmul0', 1) schedule.show(title='Improved schedule') .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_002.png :alt: Improved schedule :srcset: /examples/images/sphx_glr_folding_example_with_architecture_002.png :class: sphx-glr-single-img .. GENERATED FROM PYTHON SOURCE LINES 71-72 Extract operations and create processing elements .. GENERATED FROM PYTHON SOURCE LINES 72-87 .. code-block:: Python operations = schedule.get_operations() adders = operations.get_by_type_name('add') adders.show(title="Adder executions") mults = operations.get_by_type_name('cmul') mults.show(title="Multiplier executions") inputs = operations.get_by_type_name('in') inputs.show(title="Input executions") outputs = operations.get_by_type_name('out') outputs.show(title="Output executions") p1 = ProcessingElement(adders, entity_name="adder") p2 = ProcessingElement(mults, entity_name="cmul") p_in = ProcessingElement(inputs, entity_name='input') p_out = ProcessingElement(outputs, entity_name='output') .. rst-class:: sphx-glr-horizontal * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_003.png :alt: Adder executions :srcset: /examples/images/sphx_glr_folding_example_with_architecture_003.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_004.png :alt: Multiplier executions :srcset: /examples/images/sphx_glr_folding_example_with_architecture_004.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_005.png :alt: Input executions :srcset: /examples/images/sphx_glr_folding_example_with_architecture_005.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_006.png :alt: Output executions :srcset: /examples/images/sphx_glr_folding_example_with_architecture_006.png :class: sphx-glr-multi-img .. GENERATED FROM PYTHON SOURCE LINES 88-89 Extract and assign memory variables .. GENERATED FROM PYTHON SOURCE LINES 89-105 .. code-block:: Python mem_vars = schedule.get_memory_variables() mem_vars.show(title="All memory variables") direct, mem_vars = mem_vars.split_on_length() mem_vars.show(title="Non-zero time memory variables") mem_vars_set = mem_vars.split_on_ports(read_ports=1, write_ports=1, total_ports=2) memories = [] for i, mem in enumerate(mem_vars_set): memory = Memory(mem, memory_type="RAM", entity_name=f"memory{i}") memories.append(memory) mem.show(title=f"{memory.entity_name}") memory.assign("left_edge") memory.show_content(title=f"Assigned {memory.entity_name}") direct.show(title="Direct interconnects") .. rst-class:: sphx-glr-horizontal * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_007.png :alt: All memory variables :srcset: /examples/images/sphx_glr_folding_example_with_architecture_007.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_008.png :alt: Non-zero time memory variables :srcset: /examples/images/sphx_glr_folding_example_with_architecture_008.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_009.png :alt: memory0 :srcset: /examples/images/sphx_glr_folding_example_with_architecture_009.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_010.png :alt: Assigned memory0 :srcset: /examples/images/sphx_glr_folding_example_with_architecture_010.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_011.png :alt: memory1 :srcset: /examples/images/sphx_glr_folding_example_with_architecture_011.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_012.png :alt: Assigned memory1 :srcset: /examples/images/sphx_glr_folding_example_with_architecture_012.png :class: sphx-glr-multi-img * .. image-sg:: /examples/images/sphx_glr_folding_example_with_architecture_013.png :alt: Direct interconnects :srcset: /examples/images/sphx_glr_folding_example_with_architecture_013.png :class: sphx-glr-multi-img .. GENERATED FROM PYTHON SOURCE LINES 106-107 Create architecture .. GENERATED FROM PYTHON SOURCE LINES 107-109 .. code-block:: Python arch = Architecture({p1, p2, p_in, p_out}, memories, direct_interconnects=direct) .. GENERATED FROM PYTHON SOURCE LINES 110-111 The architecture can be rendered in enriched shells. .. GENERATED FROM PYTHON SOURCE LINES 111-112 .. code-block:: Python arch .. raw:: html
%3 cluster_memories Memories cluster_pes Processing Elements cluster_io I/O memory0 in0 memory0: (RAM, 2 cells) out0 memory0out0_branch memory0:out0->memory0out0_branch memory1 in0 memory1: (RAM, 1 cell) out0 adder_in1_mux in0 in1 in2 adder_in1_mux out0 memory1:out0->adder_in1_mux:in0 1 adder in0 in1 adder out0 adderout0_branch adder:out0->adderout0_branch cmul in0 cmul out0 cmulout0_branch cmul:out0->cmulout0_branch output in0 output input input out0 adder_in0_mux in0 in1 in2 adder_in0_mux out0 input:out0->adder_in0_mux:in1 1 adder_in0_mux:out0->adder:in0 adder_in1_mux:out0->adder:in1 memory0_in0_mux in0 in1 memory0_in0_mux out0 memory0_in0_mux:out0->memory0:in0 cmul_in0_mux in0 in1 cmul_in0_mux out0 cmul_in0_mux:out0->cmul:in0 adderout0_branch->output:in0 1 adderout0_branch->adder_in1_mux:in1 2 adderout0_branch->memory0_in0_mux:in1 1 adderout0_branch->cmul_in0_mux:in0 1 memory0out0_branch->adder_in0_mux:in2 1 memory0out0_branch->adder_in1_mux:in2 1 memory0out0_branch->cmul_in0_mux:in1 3 cmulout0_branch->memory1:in0 1 cmulout0_branch->adder_in0_mux:in0 2 cmulout0_branch->memory0_in0_mux:in0 1


.. rst-class:: sphx-glr-timing **Total running time of the script:** (0 minutes 1.481 seconds) .. _sphx_glr_download_examples_folding_example_with_architecture.py: .. only:: html .. container:: sphx-glr-footer sphx-glr-footer-example .. container:: sphx-glr-download sphx-glr-download-jupyter :download:`Download Jupyter notebook: folding_example_with_architecture.ipynb ` .. container:: sphx-glr-download sphx-glr-download-python :download:`Download Python source code: folding_example_with_architecture.py ` .. container:: sphx-glr-download sphx-glr-download-zip :download:`Download zipped: folding_example_with_architecture.zip ` .. only:: html .. rst-class:: sphx-glr-signature `Gallery generated by Sphinx-Gallery `_