`b_asic.architecture`¶

B-ASIC architecture classes.

class b_asic.architecture.Architecture(processing_elements: ProcessingElement | Iterable[ProcessingElement], memories: Memory | Iterable[Memory], entity_name: str = 'arch', direct_interconnects: ProcessCollection | None = None)¶

Class representing an architecture.

Parameters:

processing_elementsProcessingElement or iterable of ProcessingElement: The processing elements in the architecture.
memoriesMemory or iterable of Memory: The memories in the architecture.
entity_namestr, default: “arch”: Name for the top-level entity.
direct_interconnectsProcessCollection, optional: Process collection of zero-time memory variables used for direct interconnects.

add_resource(resource: Resource) → None¶

Add a new Resource to the architecture.

Parameters:

resourceResource: The resource to add.

assign_resources(strategy: Literal['left_edge'] = 'left_edge') → None¶

Assign all resources in the architecture.

Parameters:

strategystr, default: “left_edge”: The heurstic to use.

See also

Memory.assign
ProcessingElement.assign

property direct_interconnects: ProcessCollection | None¶

property entity_name: str¶

get_interconnects_for_memory(mem: Memory | str) → tuple[dict[Resource, int], dict[Resource, int]]¶

Return a dictionary with interconnect information for a Memory.

Parameters:

memMemory or str: The memory or entity name to obtain information about.

Returns:

(dict, dict): A dictionary with the ProcessingElements that are connected to the read and write ports, respectively, with counts of the number of accesses.

get_interconnects_for_pe(pe: str | ProcessingElement) → tuple[list[dict[tuple[Resource, int], int]], list[dict[tuple[Resource, int], int]]]¶

Return with interconnect information for a ProcessingElement.

The information is tuple, where each element is a lists of dictionaries.

Parameters:

peProcessingElement or str: The processing element or entity name to get information for.

Returns:

list: List of dictionaries indicating the sources for each input port and the frequency of accesses.
list: List of dictionaries indicating the destinations for each output port and the frequency of accesses.

property memories: list[Memory]¶

move_process(proc: str | Process, source: str | Resource, destination: str | Resource, assign: bool = False) → None¶

Move a Process from one Resource to another.

Both the resource moved from and will become unassigned after a process has been moved, unless assign is True.

Parameters:

procProcess or str: The process (or its name) to move.
sourceResource or str: The resource (or its entity name) to move the process from.
destinationResource or str: The resource (or its entity name) to move the process to.
assignbool, default=False: Whether to perform assignment of the resources after moving.

Raises:

KeyError: If proc is not present in resource source.

property processing_elements: list[ProcessingElement]¶

remove_resource(resource: str | Resource) → None¶

Remove an empty Resource from the architecture.

Parameters:

resourceResource or str: The resource or the resource name to remove.

resource_from_name(name: str) → Resource¶

Get Resource based on name.

Parameters:

namestr: Name of the resource.

Returns:

Resource

property schedule_time: int¶: The schedule time for hardware block.

set_entity_name(entity_name: str) → None¶

Set entity name of hardware block.

Parameters:

entity_namestr: The entity name.

show(fmt: str | None = None, branch_node: bool = True, cluster: bool = True, splines: Literal['spline', 'line', 'ortho', 'polyline', 'curved'] = 'spline', io_cluster: bool = True, multiplexers: bool = True, colored: bool = True) → None¶

Display a visual representation of the Architecture using the default system viewer.

Parameters:

fmtstr, optional: File format of the generated graph. Output formats can be found at https://www.graphviz.org/doc/info/output.html Most common are “pdf”, “eps”, “png”, and “svg”. Default is None which leads to PDF.
branch_nodebool, default: True: Whether to create a branch node for outputs with fan-out of two or higher.
clusterbool, default: True: Whether to draw memories and PEs in separate clusters.
splines{“spline”, “line”, “ortho”, “polyline”, “curved”}, default: “spline”: Spline style, see https://graphviz.org/docs/attrs/splines/ for more info.
io_clusterbool, default: True: Whether Inputs and Outputs are drawn inside an IO cluster. Only relevant if cluster is True.
multiplexersbool, default: True: Whether input multiplexers are included.
coloredbool, default: True: Whether to color the nodes.

validate_ports() → None¶

write_component_declaration(f: TextIO, dt: VhdlDataType, indent: int = 1) → None¶

Write component declaration of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the declaration to.
indentint, default: 1: Indentation level to use for this process.

write_component_instantiation(f: TextIO, dt: VhdlDataType, indent: int = 1) → None¶

Write component instantiation of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the instantiation to.
indentint, default: 1: Indentation level to use for this process.

write_signal_declarations(f: TextIO, dt: VhdlDataType, indent: int = 1) → None¶

class b_asic.architecture.ControlTable(name: str, wl: tuple[int, int], values: dict[int, int], is_signed: bool)¶

Control table for PEs.

One control table per PE parameter is generated as part of the code generation.

Parameters:

namestr: The parameter name.
wl(int, int): Word length specification.
valuesdict(int, int): Dictionary with clock cycle and bit pattern.
is_signed: bool: Whether the parameter is signed or unsigned.

property bits: int¶

property frac_bits: int¶

get_static_value() → int¶

property int_bits: int¶

is_signed: bool¶

property is_static: bool¶

name: str¶

property number_of_different_values: int¶

values: dict[int, int]¶

wl: tuple[int, int]¶

class b_asic.architecture.HardwareBlock(entity_name: str | None = None)¶

Base class for architectures and resources.

Parameters:

entity_namestr, optional: The name of the resulting entity.

property entity_name: str¶

property schedule_time: int¶: The schedule time for hardware block.

set_entity_name(entity_name: str) → None¶

Set entity name of hardware block.

Parameters:

entity_namestr: The entity name.

abstractmethod write_component_declaration(f: TextIO, indent: int = 1) → None¶

Write component declaration of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the declaration to.
indentint, default: 1: Indentation level to use for this process.

abstractmethod write_component_instantiation(f: TextIO, indent: int = 1) → None¶

Write component instantiation of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the instantiation to.
indentint, default: 1: Indentation level to use for this process.

class b_asic.architecture.Memory(process_collection: ProcessCollection, memory_type: Literal['RAM', 'register'] = 'RAM', entity_name: str | None = None, read_ports: int | None = None, write_ports: int | None = None, total_ports: int | None = None, assign: bool = False)¶

Create a memory from a ProcessCollection with memory variables.

Parameters:

process_collectionProcessCollection: The ProcessCollection to create a Memory for.
memory_type{‘RAM’, ‘register’}: The type of memory.
entity_namestr, optional: Name of memory entity.
read_portsint, optional: Number of read ports for memory.
write_portsint, optional: Number of write ports for memory.
total_portsint, optional: Total number of read and write ports for memory.
assignbool, default False: Perform assignment when creating the Memory (using the default properties).

add_process(proc: Process, assign=False) → None¶

Add a Process to this Resource.

Parameters:

procProcess: The process to add.
assignbool, default=False: Whether to perform assignment of the resource after adding.

Raises:

TypeError: If the process being added is not of the same type as the other processes.

assign(strategy: Literal['left_edge', 'greedy_graph_color', 'ilp_graph_color'] = 'left_edge', **kwargs) → None¶

Perform assignment of the memory variables.

Parameters:

strategystr, default: ‘left_edge’

The assignment algorithm. Depending on memory type the following are available:

‘RAM’
- ‘left_edge’: Left-edge algorithm.
- ‘greedy_graph_color’: Greedy graph-coloring based on exclusion graph.
- ‘ilp_graph_color’: Optimal graph-coloring based on exclusion graph.
‘register’
- …

**kwargsdict

Additional keyword arguments are passed to ~ProcessCollection.split_on_execution_time.

See also

ProcessCollection.split_on_execution_time

property assignment: list[ProcessCollection] | None¶

property collection: ProcessCollection¶

property content: Figure¶

Return a graphical representation of the content.

This is visible in enriched shells, but the object itself has no further meaning (it is a Matplotlib Figure).

property entity_name: str¶

property input_count: int¶: Number of input ports.

property is_assigned: bool¶

property operation_type: type[MemoryProcess]¶

property output_count: int¶: Number of output ports.

plot_content(ax: Axes, **kwargs) → None¶

Plot the content of the resource.

This plots the assigned processes executed on this resource.

Parameters:

axAxes: Matplotlib Axes to plot in.
**kwargs: Passed to plot().

remove_process(proc: Process, assign: bool = False) → None¶

Remove a Process from this Resource.

Raises KeyError if the process being added is not of the same type as the other processes.

Parameters:

procProcess: The process to remove.
assignbool, default=False: Whether to perform assignment of the resource after removal.

Raises:

KeyError: If proc is not present in resource.

property schedule_time: int¶: The schedule time for hardware block.

set_entity_name(entity_name: str) → None¶

Set entity name of hardware block.

Parameters:

entity_namestr: The entity name.

show_content(title=None, **kwargs) → None¶

Display the content of the resource.

This displays the assigned processes executed on this resource.

Parameters:

titlestr, optional: Figure title.
**kwargs: Passed to plot().

write_component_declaration(f: TextIO, dt: DataType, indent: int = 1) → None¶

Write component declaration of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the declaration to.
indentint, default: 1: Indentation level to use for this process.

write_component_instantiation(f: TextIO, indent: int = 1) → None¶

Write component instantiation of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the instantiation to.
indentint, default: 1: Indentation level to use for this process.

write_signal_declarations(f: TextIO, dt: DataType, indent: int = 1) → None¶

class b_asic.architecture.ProcessingElement(process_collection: ProcessCollection, entity_name: str | None = None, assign: bool = True)¶

Create a processing element for a ProcessCollection with OperatorProcesses.

Parameters:

process_collectionProcessCollection: Process collection containing operations to map to processing element.
entity_namestr, optional: Name of processing element entity.
assignbool, default True: Perform assignment when creating the ProcessingElement.

add_process(proc: Process, assign=False) → None¶

Add a Process to this Resource.

Parameters:

procProcess: The process to add.
assignbool, default=False: Whether to perform assignment of the resource after adding.

Raises:

TypeError: If the process being added is not of the same type as the other processes.

assign(strategy: Literal['left_edge', 'greedy_graph_color', 'ilp_graph_color'] = 'left_edge', **kwargs) → None¶

Perform assignment of the processes.

Parameters:

strategy{‘left_edge’, ‘greedy_graph_color’, ‘ilp_graph_color’}, default: ‘left_edge’

The assignment algorithm.

‘left_edge’: Left-edge algorithm.
‘greedy_graph_color’: Greedy graph-coloring based on exclusion graph.
‘ilp_graph_color’: Optimal graph-coloring based on exclusion graph.

**kwargsdict

Additional keyword arguments are passed to ~ProcessCollection.split_on_execution_time.

See also

ProcessCollection.split_on_execution_time

property assignment: list[ProcessCollection] | None¶

property collection: ProcessCollection¶

property content: Figure¶

Return a graphical representation of the content.

This is visible in enriched shells, but the object itself has no further meaning (it is a Matplotlib Figure).

property control_table: dict[str, ControlTable]¶

property entity_name: str¶

property input_count: int¶: Number of input ports.

property is_assigned: bool¶

property operation_type: type[Operation]¶

property output_count: int¶: Number of output ports.

plot_content(ax: Axes, **kwargs) → None¶

Plot the content of the resource.

This plots the assigned processes executed on this resource.

Parameters:

axAxes: Matplotlib Axes to plot in.
**kwargs: Passed to plot().

property processes: list[OperatorProcess]¶

remove_process(proc: Process, assign: bool = False) → None¶

Remove a Process from this Resource.

Raises KeyError if the process being added is not of the same type as the other processes.

Parameters:

procProcess: The process to remove.
assignbool, default=False: Whether to perform assignment of the resource after removal.

Raises:

KeyError: If proc is not present in resource.

property schedule_time: int¶: The schedule time for hardware block.

set_entity_name(entity_name: str) → None¶

Set entity name of hardware block.

Parameters:

entity_namestr: The entity name.

show_content(title=None, **kwargs) → None¶

Display the content of the resource.

This displays the assigned processes executed on this resource.

Parameters:

titlestr, optional: Figure title.
**kwargs: Passed to plot().

write_component_declaration(f: TextIO, dt: VhdlDataType, indent: int = 1) → None¶

Write component declaration of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the declaration to.
indentint, default: 1: Indentation level to use for this process.

write_component_instantiation(f: TextIO, dt: VhdlDataType, indent: int = 1) → None¶

Write component instantiation of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the instantiation to.
indentint, default: 1: Indentation level to use for this process.

write_signal_declarations(f: TextIO, dt: VhdlDataType, indent: int = 1) → None¶

class b_asic.architecture.Resource(process_collection: ProcessCollection, entity_name: str | None = None)¶

Base class for resource.

Parameters:

process_collectionProcessCollection: The process collection containing processes to be mapped to resource.
entity_namestr, optional: The name of the resulting entity.

add_process(proc: Process, assign=False) → None¶

Add a Process to this Resource.

Parameters:

procProcess: The process to add.
assignbool, default=False: Whether to perform assignment of the resource after adding.

Raises:

TypeError: If the process being added is not of the same type as the other processes.

assign(strategy: Literal['left_edge'] = 'left_edge') → NoReturn¶

Perform assignment of processes to resource.

Parameters:

strategystr: See the specific resource types for more information.

See also

Memory.assign
ProcessingElement.assign

property assignment: list[ProcessCollection] | None¶

property collection: ProcessCollection¶

property content: Figure¶

Return a graphical representation of the content.

This is visible in enriched shells, but the object itself has no further meaning (it is a Matplotlib Figure).

property entity_name: str¶

property input_count: int¶: Number of input ports.

property is_assigned: bool¶

property operation_type: type[MemoryProcess] | type[Operation]¶

property output_count: int¶: Number of output ports.

plot_content(ax: Axes, **kwargs) → None¶

Plot the content of the resource.

This plots the assigned processes executed on this resource.

Parameters:

axAxes: Matplotlib Axes to plot in.
**kwargs: Passed to plot().

remove_process(proc: Process, assign: bool = False) → None¶

Remove a Process from this Resource.

Raises KeyError if the process being added is not of the same type as the other processes.

Parameters:

procProcess: The process to remove.
assignbool, default=False: Whether to perform assignment of the resource after removal.

Raises:

KeyError: If proc is not present in resource.

property schedule_time: int¶: The schedule time for hardware block.

set_entity_name(entity_name: str) → None¶

Set entity name of hardware block.

Parameters:

entity_namestr: The entity name.

show_content(title=None, **kwargs) → None¶

Display the content of the resource.

This displays the assigned processes executed on this resource.

Parameters:

titlestr, optional: Figure title.
**kwargs: Passed to plot().

abstractmethod write_component_declaration(f: TextIO, indent: int = 1) → None¶

Write component declaration of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the declaration to.
indentint, default: 1: Indentation level to use for this process.

abstractmethod write_component_instantiation(f: TextIO, indent: int = 1) → None¶

Write component instantiation of hardware block.

Parameters:

fTextIO: File object (or other TextIO object) to write the instantiation to.
indentint, default: 1: Indentation level to use for this process.

b_asic.architecture¶

`b_asic.architecture`¶