b_asic.code_printer.vhdl

B-ASIC code generation helper module for VHDL.

common module

Generation of common VHDL constructs.

b_asic.code_printer.vhdl.common.alias_declaration(f: TextIO, name: str, signal_type: str, value: str | None = None, name_pad: int | None = None) → None

b_asic.code_printer.vhdl.common.asynchronous_read_memory(f: TextIO, clk: str, read_ports: set[tuple[str, str, str]], write_ports: set[tuple[str, str, str]], name: str | None = None) → None

Infer a VHDL memory with synchronous writes and asynchronous reads.

Parameters:

fTextIO

The TextIO to write the VHDL code onto.

clkstr

Name of clock identifier to the synchronous memory.

read_portsSet[Tuple[str,str]]

A set of strings used as identifiers for the read ports of the memory.

write_portsSet[Tuple[str,str,str]]

A set of strings used as identifiers for the write ports of the memory.

namestr, optional

An optional name for the memory process.

b_asic.code_printer.vhdl.common.b_asic_preamble(f: TextIO) → None

Write a standard B-ASIC VHDL preamble comment.

Parameters:

fTextIO

The file object to write the header to.

b_asic.code_printer.vhdl.common.blank(f: TextIO) → None

Write a blank line.

Parameters:

fTextIO

The file object to emit VHDL code to.

b_asic.code_printer.vhdl.common.component_declaration(f: TextIO, entity_name: str, generics: list[str] | None = None, ports: list[str] | None = None, indent: int = 1) → None

b_asic.code_printer.vhdl.common.component_instantiation(f: TextIO, label: str, entity_name: str, generic_mappings: list[str] | None = None, port_mappings: list[str] | None = None, indent: int = 1) → None

b_asic.code_printer.vhdl.common.constant_declaration(f: TextIO, name: str, signal_type: str, value: Any, name_pad: int | None = None) → None

Write a VHDL constant declaration with a name, a type and a value.

Parameters:

fTextIO

The TextIO object to write the constant declaration to.

namestr

Signal name.

signal_typestr

Signal type.

valueanything convertible to str

Default value to the signal.

name_padint, optional

An optional left padding value applied to the name.

b_asic.code_printer.vhdl.common.entity_declaration(f: TextIO, entity_name: str, generics: list[str] | None = None, ports: list[str] | None = None, indent: int = 0) → None

b_asic.code_printer.vhdl.common.ieee_header(f: TextIO, std_logic_1164: bool = True, numeric_std: bool = True, fixed_pkg: bool = False) → None

Write the standard IEEE VHDL use header.

This includes std_logic_1164 and numeric_std.

Parameters:

fTextIO

The TextIO object to write the IEEE header to.

std_logic_1164bool, default: True

Include the std_logic_1164 header.

numeric_stdbool, default: True

Include the numeric_std header.

fixed_pkgbool, default: False

Include the fixed_pkg header.

b_asic.code_printer.vhdl.common.is_valid_vhdl_identifier(identifier: str) → bool

Test if identifier is a valid VHDL identifier, as specified by VHDL 2019.

An identifier is a valid VHDL identifier if it is not a VHDL reserved keyword and it is a valid basic identifier as specified by IEEE STD 1076-2019 (VHDL standard).

Parameters:

identifierstr

The identifier to test.

Returns:

Returns True if identifier is a valid VHDL identifier, False otherwise.

b_asic.code_printer.vhdl.common.is_vhdl_reserved_keyword(identifier: str) → bool

Test if identifier is a reserved VHDL keyword.

Parameters:

identifierstr

The identifier to test.

Returns:

Returns True if identifier is reserved, False otherwise.

b_asic.code_printer.vhdl.common.package_header(f: TextIO, package_name: str) → None

b_asic.code_printer.vhdl.common.process_epilogue(f: TextIO, sensitivity_list: str | None = None, indent: int = 1, name: str | None = None) → None

Write the epilogue of a regular VHDL process.

Parameters:

fTextIO

The TextIO object to write the type declaration to.

sensitivity_liststr, optional

Content of the process sensitivity list. Not needed when writing the epilogue.

indentint, default: 1

Indentation level to use for this process.

indentint, default: 1

Indentation level to use for this process.

namestr, optional

An optional name of the ending process.

b_asic.code_printer.vhdl.common.process_prologue(f: TextIO, sensitivity_list: str, indent: int = 1, name: str | None = None) → None

Write the prologue of a regular VHDL process with a user provided sensitivity list.

This method should almost always be followed by a process_epilogue().

Parameters:

fTextIO

The TextIO object to write the type declaration to.

sensitivity_liststr

Content of the process sensitivity list.

indentint, default: 1

Indentation level to use for this process.

namestr, optional

An optional name for the process.

b_asic.code_printer.vhdl.common.signal_declaration(f: TextIO, name: str, signal_type: str, default_value: str | None = None, indent: int = 1, name_pad: int | None = None, vivado_ram_style: Literal['block', 'distributed', 'registers', 'ultra', 'mixed', 'auto'] | None = None, quartus_ram_style: Literal['M4K', 'M9K', 'M10K', 'M20K', 'M144K', 'MLAB', 'logic'] | None = None) → None

Create a VHDL signal declaration.

The declaration looks like:

signal {name} : {type} [:= {default_value}];

Parameters:

fTextIO

The TextIO object to write the IEEE header to.

namestr

Signal name.

signal_typestr

Signal type.

indentint, optional

Indentation level to use for this process.

default_valuestr, optional

An optional default value to the signal.

name_padint, optional

An optional left padding value applied to the name.

vivado_ram_stylestr, optional

An optional Xilinx Vivado RAM style attribute to apply to this signal declaration. If set, exactly one of: “block”, “distributed”, “registers”, “ultra”, “mixed” or “auto”.

quartus_ram_stylestr, optional

An optional Quartus Prime RAM style attribute to apply to this signal declaration. If set, exactly one of: “M4K”, “M9K”, “M10K”, “M20K”, “M144K”, “MLAB” or “logic”.

b_asic.code_printer.vhdl.common.synchronous_memory(f: TextIO, clk: str, read_ports: set[tuple[str, str, str]], write_ports: set[tuple[str, str, str]], name: str | None = None) → None

Infer a VHDL synchronous reads and writes.

Parameters:

fTextIO

The TextIO to write the VHDL code onto.

clkstr

Name of clock identifier to the synchronous memory.

read_portsSet[Tuple[str,str]]

A set of strings used as identifiers for the read ports of the memory.

write_portsSet[Tuple[str,str,str]]

A set of strings used as identifiers for the write ports of the memory.

namestr, optional

An optional name for the memory process.

b_asic.code_printer.vhdl.common.synchronous_process(f: TextIO, clk: str, body: str, indent: int = 1, name: str | None = None) → None

Write a regular VHDL synchronous process with a single clock.

The clock is the only item in the sensitivity list and is triggering a rising edge block by some body of VHDL code.

Parameters:

fTextIO

The TextIO to write the VHDL code onto.

clkstr

Name of the clock.

bodystr

Body of the if rising_edge(clk) then block.

indentint, default: 1

Indentation level to use for this process.

namestr, optional

An optional name for the process.

b_asic.code_printer.vhdl.common.synchronous_process_epilogue(f: TextIO, clk: str | None = None, indent: int = 1, name: str | None = None) → None

Write the epilogue of a regular VHDL synchronous process with a single clock.

The clock is the only item in the sensitivity list and is triggering a rising edge block by some body of VHDL code.

Parameters:

fTextIO

The TextIO to write the VHDL code onto.

clkstr, optional

Name of the clock.

indentint, default: 1

Indentation level to use for this process.

namestr, optional

An optional name for the process.

b_asic.code_printer.vhdl.common.synchronous_process_prologue(f: TextIO, clk: str = 'clk', indent: int = 1, name: str | None = None) → None

Write the prologue of a regular VHDL synchronous process with a single clock object.

The clock is the only item in the sensitivity list and is triggering a rising edge block by some body of VHDL code.

This method is almost always followed by a synchronous_process_epilogue().

Parameters:

fTextIO

The TextIO to write the VHDL code onto.

clkstr

Name of the clock.

indentint, default: 1

Indentation level to use for this process.

namestr, optional

An optional name for the process.

b_asic.code_printer.vhdl.common.type_declaration(f: TextIO, name: str, alias: str) → None

Write a VHDL type declaration with a name tied to an alias.

Parameters:

fTextIO

The TextIO object to write the type declaration to.

namestr

Type name alias.

aliasstr

The type to tie the new name to.

b_asic.code_printer.vhdl.common.write(f: TextIO, indent_level: int, text: str, *, end: str = '\n', start: str | None = None) → None

Write text to a VHDL file.

First, f'{VHDL_TAB*indent_level}' is written to f as indentation. Immediately after the indentation, text is written to f. Finally, text is also written to f.

Parameters:

fTextIO

The file object to emit VHDL code to.

indent_levelint

Indentation level to use. Exactly f'{VHDL_TAB*indent_level}' is written before the text is written.

textstr

The text to write to.

endstr, default: ‘n’

Text to write exactly after text is written to f.

startstr, optional

Text to write before both indentation and text.

b_asic.code_printer.vhdl.common.write_lines(f: TextIO, lines: list[tuple[int, str] | tuple[int, str, str]]) → None

Write provided lines to a VHDL file.

Each tuple (int, str, [int]) in the list lines is written to the TextIO object f using the vhdl.write() function.

Parameters:

fTextIO

The file object to emit VHDL code to.

lineslist of tuple (int,str) [1], or list of tuple (int,str,str) [2]

[1]: The first int of the tuple is used as indentation level for the line

and the second str of the tuple is the content of the line.

[2]: Same as [1], but the third str of the tuple is passed to parameter

end when calling vhdl.write().

memory_storage module

Module for VHDL code generation of memory based storage.

b_asic.code_printer.vhdl.memory_storage.architecture(f: TextIO, memory: Memory, dt: VhdlDataType, *, input_sync: bool = True, output_sync: bool = True, adr_mux_size: int = 1, adr_pipe_depth: int = 0, vivado_ram_style: Literal['block', 'distributed', 'registers', 'ultra', 'mixed', 'auto'] | None = None, quartus_ram_style: Literal['M4K', 'M9K', 'M10K', 'M20K', 'M144K', 'MLAB', 'logic'] | None = None) → None

Generate the VHDL architecture for a memory-based storage architecture.

Settings should be sanitized when calling this function, e.g. from calling generate_memory_based_storage_vhdl from one of the memory classes.

Parameters:

fTextIO

File object (or other TextIO object) to write the architecture onto.

memoryMemory

Memory object to generate code for.

dtDataType

Meta information of data signals.

input_syncbool, default: True

Add registers to the input signals (enable signal and data input signals). Adding registers to the inputs allow pipelining of address generation (which is added automatically). For large interleavers, this can improve timing significantly.

output_syncbool, default: True

Add registers to the output signal.

adr_mux_sizeint, default: 1

Size of multiplexer if using address generation pipelining. Set to 1 for no multiplexer pipelining. If any other value than 1, input_sync must be set.

adr_pipe_depthint, default: 0

Depth of address generation pipelining. Set to 0 for no multiplexer pipelining. If any other value than 0, input_sync must be set.

vivado_ram_stylestr, optional

An optional Xilinx Vivado RAM style attribute to apply to this memory. If set, exactly one of: “block”, “distributed”, “registers”, “ultra”, “mixed” or “auto”.

quartus_ram_stylestr, optional

An optional Quartus Prime RAM style attribute to apply to this memory. If set, exactly one of: “M4K”, “M9K”, “M10K”, “M20K”, “M144K”, “MLAB” or “logic”.

b_asic.code_printer.vhdl.memory_storage.entity(f: TextIO, mem: Memory, dt: VhdlDataType) → None

processing_element module

Module for VHDL code generation of processing elements.

b_asic.code_printer.vhdl.processing_element.architecture(f: TextIO, pe: ProcessingElement, dt: VhdlDataType, core_code: tuple[str, str]) → None

b_asic.code_printer.vhdl.processing_element.entity(f: TextIO, pe: ProcessingElement, dt: VhdlDataType) → None

register_storage module

Module for VHDL code generation of register based storage.

b_asic.code_printer.vhdl.register_storage.architecture(f: TextIO, forward_backward_table: _ForwardBackwardTable, memory: Memory, sync_rst: bool = False, async_rst: bool = False) → None

b_asic.code_printer.vhdl.register_storage.entity(f: TextIO, memory: Memory, dt: VhdlDataType) → None

test_bench module

Module for VHDL code generation of test benches.

b_asic.code_printer.vhdl.test_bench.architecture(f: TextIO, arch: Architecture, dt: VhdlDataType) → None

b_asic.code_printer.vhdl.test_bench.entity(f: TextIO, arch: Architecture) → None

top_level module

Module for VHDL code generation of top level designs.

b_asic.code_printer.vhdl.top_level.architecture(f: TextIO, arch: Architecture, dt: VhdlDataType) → None

b_asic.code_printer.vhdl.top_level.entity(f: TextIO, arch: Architecture, dt: VhdlDataType) → None

util module

Utility functions for VHDL Printer.

b_asic.code_printer.vhdl.util.schedule_time_type(time: int) → str

b_asic.code_printer.vhdl.util.signed_type(bits: int) → str

b_asic.code_printer.vhdl.util.unsigned_type(bits: int) → str