`b_asic.codegen.vhdl`¶

`common` module¶

Generation of common VHDL constructs

b_asic.codegen.vhdl.common.alias_declaration(f: TextIO, name: str, signal_type: str, value: str | None = None, name_pad: int | None = None)¶

b_asic.codegen.vhdl.common.asynchronous_read_memory(f: TextIO, clk: str, read_ports: Set[Tuple[str, str, str]], write_ports: Set[Tuple[str, str, str]], name: str | None = None)¶

Infer a VHDL memory with synchronous writes and asynchronous reads.

Parameters:

fTextIO: The TextIO to write the VHDL code onto.
clkstr: Name of clock identifier to the synchronous memory.
read_portsSet[Tuple[str,str]]: A set of strings used as identifiers for the read ports of the memory.
write_portsSet[Tuple[str,str,str]]: A set of strings used as identifiers for the write ports of the memory.
namestr, optional: An optional name for the memory process.

b_asic.codegen.vhdl.common.b_asic_preamble(f: TextIO)¶

Write a standard BASIC VHDL preamble comment.

Parameters:

fTextIO: The file object to write the header to.

b_asic.codegen.vhdl.common.constant_declaration(f: TextIO, name: str, signal_type: str, value: Any, name_pad: int | None = None)¶

Write a VHDL constant declaration with a name, a type and a value.

Parameters:

fTextIO: The TextIO object to write the constant declaration to.
namestr: Signal name.
signal_typestr: Signal type.
valueanything convertible to str: Default value to the signal.
name_padint, optional: An optional left padding value applied to the name.

b_asic.codegen.vhdl.common.ieee_header(f: TextIO, std_logic_1164: bool = True, numeric_std: bool = True)¶

Write the standard IEEE VHDL use header.

This includes std_logic_1164 and numeric_std.

Parameters:

fTextIO: The TextIO object to write the IEEE header to.
std_logic_1164bool, default: True: Include the std_logic_1164 header.
numeric_stdbool, default: True: Include the numeric_std header.

b_asic.codegen.vhdl.common.is_valid_vhdl_identifier(identifier: str) → bool¶

Test if identifier is a valid VHDL identifier, as specified by VHDL 2019.

An identifier is a valid VHDL identifier if it is not a VHDL reserved keyword and it is a valid basic identifier as specified by IEEE STD 1076-2019 (VHDL standard).

Parameters:

identifierstr: The identifier to test.

Returns:

Returns True if identifier is a valid VHDL identifier, False otherwise.

b_asic.codegen.vhdl.common.is_vhdl_reserved_keyword(identifier: str) → bool¶

Test if identifier is a reserved VHDL keyword.

Parameters:

identifierstr: The identifier to test.

Returns:

Returns True if identifier is reserved, False otherwise.

b_asic.codegen.vhdl.common.process_epilogue(f: TextIO, sensitivity_list: str | None = None, indent: int = 1, name: str | None = None)¶

Write the epilogue of a regular VHDL process.

Parameters:

fTextIO: The TextIO object to write the type declaration to.
sensitivity_liststr, optional: Content of the process sensitivity list. Not needed when writing the epilogue.
indentint, default: 1: Indentation level to use for this process.
indentint, default: 1: Indentation level to use for this process.
namestr, optional: An optional name of the ending process.

b_asic.codegen.vhdl.common.process_prologue(f: TextIO, sensitivity_list: str, indent: int = 1, name: str | None = None)¶

Write the prologue of a regular VHDL process with a user provided sensitivity list.

This method should almost always be followed by a process_epilogue().

Parameters:

fTextIO: The TextIO object to write the type declaration to.
sensitivity_liststr: Content of the process sensitivity list.
indentint, default: 1: Indentation level to use for this process.
namestr, optional: An optional name for the process.

b_asic.codegen.vhdl.common.signal_declaration(f: TextIO, name: str, signal_type: str, default_value: str | None = None, name_pad: int | None = None, vivado_ram_style: str | None = None, quartus_ram_style: str | None = None)¶

Create a VHDL signal declaration.

The declaration looks like:

signal {name} : {type} [:= {default_value}];

Parameters:

fTextIO: The TextIO object to write the IEEE header to.
namestr: Signal name.
signal_typestr: Signal type.
default_valuestr, optional: An optional default value to the signal.
name_padint, optional: An optional left padding value applied to the name.
vivado_ram_stylestr, optional: An optional Xilinx Vivado RAM style attribute to apply to this signal declaration. If set, exactly one of: “block”, “distributed”, “registers”, “ultra”, “mixed” or “auto”.
quartus_ram_stylestr, optional: An optional Quartus Prime RAM style attribute to apply to this signal declaration. If set, exactly one of: “M4K”, “M9K”, “M10K”, “M20K”, “M144K”, “MLAB” or “logic”.

b_asic.codegen.vhdl.common.synchronous_memory(f: TextIO, clk: str, read_ports: Set[Tuple[str, str, str]], write_ports: Set[Tuple[str, str, str]], name: str | None = None)¶

Infer a VHDL synchronous reads and writes.

Parameters:

fTextIO: The TextIO to write the VHDL code onto.
clkstr: Name of clock identifier to the synchronous memory.
read_portsSet[Tuple[str,str]]: A set of strings used as identifiers for the read ports of the memory.
write_portsSet[Tuple[str,str,str]]: A set of strings used as identifiers for the write ports of the memory.
namestr, optional: An optional name for the memory process.

b_asic.codegen.vhdl.common.synchronous_process(f: TextIO, clk: str, body: str, indent: int = 1, name: str | None = None)¶

Write a regular VHDL synchronous process with a single clock.

The clock is the only item in the sensitivity list and is triggering a rising edge block by some body of VHDL code.

Parameters:

fTextIO: The TextIO to write the VHDL code onto.
clkstr: Name of the clock.
bodystr: Body of the if rising_edge(clk) then block.
indentint, default: 1: Indentation level to use for this process.
namestr, optional: An optional name for the process.

b_asic.codegen.vhdl.common.synchronous_process_epilogue(f: TextIO, clk: str | None = None, indent: int = 1, name: str | None = None)¶

Write the epilogue of a regular VHDL synchronous process with a single clock.

The clock is the only item in the sensitivity list and is triggering a rising edge block by some body of VHDL code.

Parameters:

fTextIO: The TextIO to write the VHDL code onto.
clkstr, optional: Name of the clock.
indentint, default: 1: Indentation level to use for this process.
namestr, optional: An optional name for the process.

b_asic.codegen.vhdl.common.synchronous_process_prologue(f: TextIO, clk: str, indent: int = 1, name: str | None = None)¶

Write the prologue of a regular VHDL synchronous process with a single clock object.

The clock is the only item in the sensitivity list and is triggering a rising edge block by some body of VHDL code.

This method is almost always followed by a synchronous_process_epilogue().

Parameters:

fTextIO: The TextIO to write the VHDL code onto.
clkstr: Name of the clock.
indentint, default: 1: Indentation level to use for this process.
namestr, optional: An optional name for the process.

b_asic.codegen.vhdl.common.type_declaration(f: TextIO, name: str, alias: str)¶

Write a VHDL type declaration with a name tied to an alias.

Parameters:

fTextIO: The TextIO object to write the type declaration to.
namestr: Type name alias.
aliasstr: The type to tie the new name to.

`entity` module¶

Module for code generation of VHDL entity declarations

b_asic.codegen.vhdl.entity.memory_based_storage(f: TextIO, entity_name: str, collection: ProcessCollection, word_length: int)¶

b_asic.codegen.vhdl.entity.register_based_storage(f: TextIO, entity_name: str, collection: ProcessCollection, word_length: int)¶

`architecture` module¶

Module for code generation of VHDL architectures.

b_asic.codegen.vhdl.architecture.memory_based_storage(f: TextIO, assignment: List[ProcessCollection], entity_name: str, word_length: int, read_ports: int, write_ports: int, total_ports: int, *, input_sync: bool = True, adr_mux_size: int = 1, adr_pipe_depth: int = 0)¶

Generate the VHDL architecture for a memory-based storage architecture.

Settings should be sanitized when calling this function, e.g. from calling generate_memory_based_storage_vhdl from one of the memory classes.

Parameters:

fTextIO: File object (or other TextIO object) to write the architecture onto.
assignmentlist: A possible cell assignment to use when generating the memory based storage. The cell assignment is a dictionary int to ProcessCollection where the integer corresponds to the cell to assign all MemoryVariables in corresponding process collection. If unset, each MemoryVariable will be assigned to a unique cell.
entity_namestr: The entity name for the resulting HDL.
word_lengthint: Word length of the memory variable objects.
read_portsint: Number of read ports.
write_portsint: Number of write ports.
total_portsint: Total concurrent memory accesses possible.
input_syncbool, default: True: Add registers to the input signals (enable signal and data input signals). Adding registers to the inputs allow pipelining of address generation (which is added automatically). For large interleavers, this can improve timing significantly.
adr_mux_sizeint, default: 1: Size of multiplexer if using address generation pipelining. Set to 1 for no multiplexer pipelining. If any other value than 1, input_sync must be set.
adr_pipe_depthint, default: 0: Depth of address generation pipelining. Set to 0 for no multiplexer pipelining. If any other value than 0, input_sync must be set.

b_asic.codegen.vhdl.architecture.register_based_storage(f: TextIO, forward_backward_table: _ForwardBackwardTable, entity_name: str, word_length: int, read_ports: int, write_ports: int, total_ports: int, sync_rst: bool = False, async_rst: bool = False)¶

b_asic.codegen.vhdl¶

common module¶

entity module¶

architecture module¶

`b_asic.codegen.vhdl`¶

`common` module¶

`entity` module¶

`architecture` module¶